Design of Low Power and Area-Efficient Memory Cell
Author:
Affiliation:
1. Chandigarh University,Dept of Electronics and Communication Engineering,Mohali,Punjab
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10009017/10009021/10009357.pdf?arnumber=10009357
Reference20 articles.
1. Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline
2. Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell
3. Internal write‐back and read‐before‐write schemes to eliminate the disturbance to the half‐selected cells in SRAMs
4. Low-Power Cache Design Using 7T SRAM Cell
5. A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
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