Development of Empirical Equations for Metal Trace Failure Prediction of Wafer Level Package Under Board Level Drop Test

Author:

Chan-Yen Chou ,Tuan-Yu Hung ,Chao-Jen Huang ,Kuo-Ning Chiang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Study on Parallel Test Approach for the Flash Burn-in Experiment in Laboratory;Journal of Physics: Conference Series;2022-04-01

2. Ultra-Thin Package Board Level Drop Impact Modeling and Validation;2019 IEEE 69th Electronic Components and Technology Conference (ECTC);2019-05

3. Prediction of Fatigue Resistance in Lead-Free Ni-Doped SAC 1205 Solder Alloys Using a Rate-Dependent Material Model and Subjected to Drop Tests;IEEE Transactions on Components, Packaging and Manufacturing Technology;2018-10

4. Reliability and failure analysis of SAC 105 and SAC 1205N lead-free solder alloys during drop test events;Microelectronics Reliability;2018-01

5. Board-Level Drop Impact Reliability of Silicon Interposer-Based 2.5-D IC Integration;IEEE Transactions on Components, Packaging and Manufacturing Technology;2016-10

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