Energy Efficient Implementation of Processing Elements for CNN Hardware Accelerator
Author:
Affiliation:
1. National Institute of Technology Goa,Department of ECE,Ponda,India
2. National Institute of Technology Goa,Department of EEE,Ponda,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10150431/10151452/10151639.pdf?arnumber=10151639
Reference26 articles.
1. Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
2. Low-Power RTL Code Generation for Advanced CNN Algorithms toward Object Detection in Autonomous Vehicles
3. High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic
4. A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
5. High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture
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