Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA-Reference-Cited by-同舟云学术

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Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA

Published:2018-07 Issue:7 Volume:26 Page:1354-1367
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Ma Yufei^ORCID,Cao Yu,Vrudhula Sarma^ORCID,Seo Jae-sun

Funder

NSF I/UCRC Center for Embedded Systems through NSF

Intel Labs

Samsung Advanced Institute of Technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://ieeexplore.ieee.org/ielaam/92/8396231/8330049-aam.pdf

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