Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Full- swing GDI technique-Reference-Cited by-同舟云学术

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Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Full- swing GDI technique

Published:2019-02 Issue: Volume: Page:
ISSN:
Container-title:2019 International Conference on Innovative Trends in Computer Engineering (ITCE)
language:
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Author:

Albadry Omnia Ali,Mohamed El-Bendary M. A.,Amer Fathy Z.,Singy Said M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8640965/8646319/08646341.pdf?arnumber=8646341

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology;Heliyon;2024-05

2. Comparative Study on 4-Bit Adders and Multipliers with Hardware Implementation;2024 7th International Conference on Devices, Circuits and Systems (ICDCS);2024-04-23

3. Design and Analysis of Low Power and High-Speed Baugh Wooley Multiplier using Modified Gate Diffusion Input Technique;2024 3rd International Conference for Innovation in Technology (INOCON);2024-03-01

4. Design and implementation of low power and area efficient hybrid AHL multiplier;AIP Conference Proceedings;2024

5. Analysis of a 10T Full Adder with a new 4T X-NOR using FD-SOI 22nm Mix-VT Technology;2023 26th International Conference on Computer and Information Technology (ICCIT);2023-12-13

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