Analysis of a 10T Full Adder with a new 4T X-NOR using FD-SOI 22nm Mix-VT Technology-Reference-Cited by-同舟云学术

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Analysis of a 10T Full Adder with a new 4T X-NOR using FD-SOI 22nm Mix-VT Technology

Published:2023-12-13 Issue: Volume:3 Page:1-5
ISSN:
Container-title:2023 26th International Conference on Computer and Information Technology (ICCIT)
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Author:

Kabir S.M Kifayat¹,Ganguly Chamak²,Arefin Khandaker Shams¹,Adity Nawrin Tamim¹,Biswas Satyendra N.³

Affiliation:

1. ULKASEMI Pvt. Limited,Circuit and System Design,Dhaka,Bangladesh

2. Primeasia University,Electrical and Electronic Engineering,Dhaka,Bangladesh

3. AUST,Dept. of EEE,Dhaka

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10440723/10440967/10441621.pdf?arnumber=10441621

Reference17 articles.

1. Low-power logic styles: CMOS versus pass-transistor logic

2. Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Full- swing GDI technique

3. Pass-transistor logic design;Taylor,2007

4. Novel low power full adder cells in 180nm CMOS technology

5. An Energy Efficient Logic Approach to Implement CMOS Full Adder

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