Reliability of SPST Series-stacked SOI CMOS RF Switches for mmWave Applications
Author:
Affiliation:
1. Indian Institute of Technology Delhi,Department of Electrical Engineering,New Delhi,India
2. GLOBALFOUNDRIES Inc,Quality and Reliability Engineering,Bangalore,India
3. GLOBALFOUNDRIES Inc,Quality and Reliability Engineering,Malta,US
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10117589/10117581/10118205.pdf?arnumber=10118205
Reference16 articles.
1. (Invited) Recent insights in CMOS reliability characterization by the use of degradation maps
2. Characterization and physical modeling of the temporal evolution of near-interfacial states resulting from NBTI/PBTI stress in nMOS/pMOS transistors
3. A 31.3-dBm Bulk CMOS T/R Switch Using Stacked Transistors With Sub-Design-Rule Channel Length in Floated p-Wells
4. A 0.5-μm CMOS T/R switch for 900-MHz wireless applications
5. Challenges in Radio Frequency and Mixed-Signal Circuit Reliability
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