Impact of Design and Process on Alpha-Induced SER in 4 nm Bulk-FinFET SRAM
Author:
Affiliation:
1. Device Solution, Samsung Electronics, Co., Ltd.,Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10117589/10117581/10117908.pdf?arnumber=10117908
Reference25 articles.
1. Investigating of SER in 28 nm FDSOI-Planar and Comparing with SER in Bulk-FinFET
2. Backside Alpha-Irradiation Test in Flip-Chip Package in EUV 7 nm FinFET SRAM
3. Development of thermal neutron SER-resilient high-k/metal gate technology
4. Charge-collection modeling for SER simulation in FinFETs
5. Technology Scaling Trend of Soft Error Rate in Flip-Flops in $1\times$ nm Bulk FinFET Technology
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1. Etching selectivity of SiO2 to SiN using HF and methanol at higher pressures up to 900 Pa;Japanese Journal of Applied Physics;2024-06-03
2. Comprehensive Study of SER in FDSOI-Planar: 28 nm to 18 nm Scaling Effect and Temperature Dependence;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
3. Soft-Error Sensitivity in SRAM Manufactured by Bulk Gate-All-Around (GAA) Technology;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
4. Design and Analysis of Static Random-Access Memory FinFET Circuit Using Self Controlled Voltage Level Controller;Journal of Nanoelectronics and Optoelectronics;2023-08-01
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