Linearity Behavior of a Pocket Doped p-type Ground Plane FDSOI: Impact of Back Biasing
Author:
Affiliation:
1. IIITDM Kancheepuram,Department of ECE,Chennai,India,600127
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9776592/9776648/09776790.pdf?arnumber=9776790
Reference20 articles.
1. 28 nm FDSOI analog and RF Figures of Merit at N2 cryogenic temperatures
2. Performance of SOI devices transferred onto passivated HR SOI substrates using a layer transfer technique
3. RF Characteristics of Two Generations of RFeSI HR-SOI Substrates Over Temperature
4. UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime
5. FDSOI devices with thin BOX and ground plane integration for 32nm node and below
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