Vertical Charge Loss Induced by Defect Coupling at SiO2/Si3N4 Interface in 3D NAND Flash Memory-Reference-Cited by-同舟云学术

Vertical Charge Loss Induced by Defect Coupling at SiO₂/Si₃N₄ Interface in 3D NAND Flash Memory

Published:2023-07-21 Issue: Volume: Page:
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Container-title:2023 IEEE 6th International Conference on Electronic Information and Communication Technology (ICEICT)
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Author:

Lv Xue¹,Yu Hongchen¹,Chen Da¹,Wang Fei¹

Affiliation:

1. College of Electronic and Information Engineering, Shandong University of Science and Technology,Qingdao,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10244769/10244774/10245489.pdf?arnumber=10245489

Reference11 articles.

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2. The analysis of a plane wave pseudopotential density functional theory code on a GPU machine

3. Physics of hole trapping process in high-k gate stacks: A direct simulation formalism for the whole interface system combining density-functional theory and Marcus theory

4. Modeling of Charge Loss Mechanisms during the Short Term Retention Operation in 3-D NAND Flash Memories

5. Characterization Summary of Performance, Reliability, and Threshold Voltage Distribution of 3D Charge-Trap NAND Flash Memory

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