Understanding and Improving Reliability for Wafer Level Chip Scale Package: A Study Based on 45nm RFSOI Technology for 5G Applications

Author:

Wu Zhuo-JieORCID,Zhang HaojunORCID,Malinowski John

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Multi-parameters optimization for electromigration in WLCSP solder bumps;2024 25th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE);2024-04-07

2. Advances and Reliability Challenges in Heterogeneous Integration in Chiplet ERA: From Solder to Copper to Optical Interconnects;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17

3. Comparative study of solder joint reliability assessment on fan-out CSP and flip-chip DCA package;Journal of Materials Science: Materials in Electronics;2023-11

4. Single Factor Study of Solder Joint Reliability for MCP Packages;2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA);2023-07-24

5. Wafer Level Chip Scale Package Failure Mode Prediction using Finite Element Modeling;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03

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