Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes-Reference-Cited by-同舟云学术

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Scaling Challenges of Nanosheet Field-Effect Transistors Into Sub-2 nm Nodes

Published:2024 Issue: Volume:12 Page:479-485
ISSN:2168-6734
Container-title:IEEE Journal of the Electron Devices Society
language:
Short-container-title:IEEE J. Electron Devices Soc.

Author:

Alabdullah Murad G. K.¹^ORCID,Elmessary M. A.²^ORCID,Nagy D.¹^ORCID,Seoane N.³^ORCID,García-Loureiro A. J.³^ORCID,Kalna K.¹^ORCID

Affiliation:

1. Department of Electronic and Electrical Engineering, Faculty of Science and Engineering, NanoDeCo Group, Swansea University, Swansea, U.K.

2. Department of Engineering Mathematics and Physics, Mansoura University, Mansoura, Egypt

3. CITIUS, University of Santiago de Compostela, Santiago de Compostela, Spain

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/6245494/10416702/10561475.pdf?arnumber=10561475

Reference45 articles.

1. Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets

2. Five nanometre CMOS technology

3. Chip Power-Frequency Scaling in 10/7nm Node

4. A new framework of physics-based compact model predicts reliability of self-heated modern ICs: FinFET, NWFET, NSHFET comparison

5. Impact of aggressive fin width scaling on FinFET device characteristics

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impacts of quantum confinement effect on threshold voltage and drain-induced barrier lowering effect of junctionless surrounding-gate nanosheet NMOSFET including source/drain depletion regions;Microelectronics Journal;2024-10

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