Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect-Reference-Cited by-同舟云学术

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Optimum repeater insertion based on a CMOS delay model for on-chip RLC interconnect

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Container-title:Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)
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Author:

Ismail Y.I.,Friedman E.G.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx4/5864/15621/00723040.pdf?arnumber=723040

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Closed-form Delay Estimation Model for Current-mode High Speed VLSI Interconnects;WSEAS TRANSACTIONS ON COMMUNICATIONS;2021-12-29

2. Buffer insertion for delay minimization in RLC interconnects using cuckoo optimization algorithm;Analog Integrated Circuits and Signal Processing;2018-09-04

3. EFFICIENT DELAY AND CROSSTALK ESTIMATION MODELS FOR CURRENT-MODE HIGH SPEED INTERCONNECTS UNDER RAMP INPUT;Journal of Circuits, Systems and Computers;2014-05-14

4. A Data Capturing Method for Buses on Chip;IEEE Transactions on Circuits and Systems I: Regular Papers;2010-07

5. Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion;Circuits, Systems and Signal Processing;2009-08-20

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