Asynchronous Circular Buffers based on FIFO for Network on Chips
Author:
Affiliation:
1. Vel Tech High Tech Dr. Rangarajan Dr. Sakunthala Engineering College, Avadi,Department of Electronics and Communication Engineering,Chennai,Tamilnadu,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10244767/10244778/10245047.pdf?arnumber=10245047
Reference15 articles.
1. Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path;zhengfan;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2015
2. Register-Less NULL Convention Logic
3. Reliability Analysis of FinFET Based High Performance Circuits
4. Design of True Random Number Circuit with Controllable Frequency
5. Novel Asynchronous Pipeline Architectures for High-Throughput Applications
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