Proposal of Vertical-channel Fin-SiC MOSFET toward Future Device Scaling

Author:

Shimizu Haruka1,Suto Takeru1,Miki Hiroshi1,Mori Yuki1,Hisamoto Digh1,Shima Akio1,Kinoshita Koyo2,Murata Tatsunori2,Oda Tetsuo2

Affiliation:

1. Hitachi, Ltd.,Research and Development Group,Kokubunji-shi, Tokyo,Japan

2. Hitachi Power Semiconductor Device, Ltd.,Hitachi-shi,Ibaraki-ken,Japan

Publisher

IEEE

Reference6 articles.

1. Device design to achieve low loss and high shortcircuit capability for SiC Trench MOSFET;mori;Proceedings on International Symposium on Power Semiconductor Devices & ICs,0

2. Novel trench-etched double-diffused SiC MOS (TED MOS) for overcoming tradeoff between RonA and Qgd;tega;Proceedings on International Symposium on Power Semiconductor Devices & ICs,0

3. Experimental demonstration, challenges, and prospects of the vertical SiC FinFET

4. The FinFET effect in Silicon Carbide MOSFETs

5. Performance and ruggedness of 1200V SiC — Trench — MOSFET

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Vertical-Channel Fin-SiC (VC Fin-SiC) With Partially Highly Doped JFET for 3.3-kV Applications;IEEE Transactions on Electron Devices;2024-09

2. Development of Vertical-Channel Fin-SiC MOSFET for 3.3 kV Applications;2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2024-06-02

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