Experimental demonstration, challenges, and prospects of the vertical SiC FinFET

Author:

Udrea F.1,Naydenov K.1,Kang H.1,Kato T.2,Kagoshima E.2,Fujioka H.2,Tomita H.2,Nishiwaki T.2,Fujiwara H.2,Kimoto T.3

Affiliation:

1. University of Cambridge,Department of Engineering,Cambridge,UK,CB3 0FA

2. MIRISE Technologies Corporation,Toyota,Japan,470-0309

3. Kyoto University,Department of Electronic Sci. & Eng.,Kyoto,Japan,615-8510

Publisher

IEEE

Reference18 articles.

1. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm;hisamoto;IEEE Transactions on Electron Devices,2000

2. Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs

3. Sentaurus Device User Guide, Synopsys,2019

4. Carrier transport properties in inversion layer of Si-face 4H–SiC MOSFET with nitrided oxide

5. Fundamentals of power semiconductor devices;baliga,2010

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2. A Discrete Channel Model to Estimate Threshold Voltage Deviation Induced by The Voltage Stress in SiC Short Channel MOSFETs;2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2024-06-02

3. Vertical GaN MOSFET Power Devices;Micromachines;2023-10-16

4. Proposal of Vertical-channel Fin-SiC MOSFET toward Future Device Scaling;2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD);2023-05-28

5. Multidimensional device architectures for efficient power electronics;Nature Electronics;2022-11-17

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