Experimental demonstration, challenges, and prospects of the vertical SiC FinFET
Author:
Affiliation:
1. University of Cambridge,Department of Engineering,Cambridge,UK,CB3 0FA
2. MIRISE Technologies Corporation,Toyota,Japan,470-0309
3. Kyoto University,Department of Electronic Sci. & Eng.,Kyoto,Japan,615-8510
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9813543/9813532/09813617.pdf?arnumber=9813617
Reference18 articles.
1. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm;hisamoto;IEEE Transactions on Electron Devices,2000
2. Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs
3. Sentaurus Device User Guide, Synopsys,2019
4. Carrier transport properties in inversion layer of Si-face 4H–SiC MOSFET with nitrided oxide
5. Fundamentals of power semiconductor devices;baliga,2010
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