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Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing

  • Published:2016-01 Issue:1 Volume:24 Page:129-138
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Patel Ravi,Guo Xiaochen,Guo Qing,Ipek Engin,Friedman Eby G.

Funder

Binational Science Foundation

National Science Foundation

New York State Office of Science and Technology

Research Grant through the IBM, Qualcomm, Cisco Systems, and Samsung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Survey On the Sensing Techniques Used for Spin Transfer Torque MRAM;Journal of The Institution of Engineers (India): Series B;2024-07-18

2. CAWPR: Contention Aware Write Preemptive Management Policy for Hybrid Last Level Caches;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19

3. Double magnetic tunnel junction two bit memory and nonvolatile logic for in situ computing;Microelectronics Journal;2023-01

4. Spin-Transfer Torque MRAM with Emerging Sensing Techniques;Lecture Notes in Electrical Engineering;2023

5. All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits;ACM Journal on Emerging Technologies in Computing Systems;2022-10-13
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