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Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching

  • Published:2017-03 Issue:3 Volume:25 Page:1168-1172
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Xing DezhiORCID,Zhu Yan,Chan Chi-Hang,Sin Sai-Weng,Ye Fan,Ren Junyan,U Seng-Pan,Martins Rui Paulo

Funder

National High-Tech Research and Development Program of China (863 Program)

Research Grants of the University of Macau

Macau Science and Technology Development Fund

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. FAPSO: Fast Adaptive Particle Swarm Optimization-Based Background Timing Skew Calibration for TI-ADCs;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-09

2. An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07

3. High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-12

4. A Novel All-Digital Calibration Method for Timing Mismatch in Time-Interleaved ADC Based on Modulation Matrix;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-07

5. A High-Speed ADC for a Multi-Band 5G V2X Wireless Receiver;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
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