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Feedforward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator

  • Published:2019-01 Issue:1 Volume:27 Page:138-146
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

Ryu SungjuORCID,Park NaebeomORCID,Kim Jae-JoonORCID

Funder

Samsung

Ministry of Science and ICT, South Korea, through the ICT Consilience Creative Program

Institute for Information and communications Technology Promotion

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07

2. Integrated MAC-based Systolic Arrays: Design and Performance Evaluation;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

3. Efficiency Evaluation of Scalable Multiply and Accumulate Architectures in DSP: A Comparative Study of LUT Based and LUT-Less Based Approaches;2024 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE);2024-01-24

4. Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies;Electronics;2023-05-10

5. Design and Analysis of High-Throughput Two-Cycle Multiply-Accumulate (MAC) Architectures for Fixed-Point Arithmetic;2022 IEEE Calcutta Conference (CALCON);2022-12-10
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