A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations-Reference-Cited by-同舟云学术

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A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations

Published:2015-11 Issue:11 Volume:23 Page:2438-2446
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Pasandi Ghasem,Fakhraie Sied Mehdi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7302619/06996023.pdf?arnumber=6996023

Cited by 56 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Low-Energy, Stable, Single-Bitline Accessed FinFET 9T-SRAM;Circuits, Systems, and Signal Processing;2024-05-20

2. Schmitter trigger-based single-ended stable 7T SRAM cell;Analog Integrated Circuits and Signal Processing;2023-09-23

3. A low-power SRAM design with enhanced stability and I_ON/I_OFF ratio in FinFET technology for wearable device applications;International Journal of Electronics;2023-07-25

4. A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-V _DD Assist and Bitline Leakage Compensation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-05

5. Review of 6T SRAM for Embedded Memory Applications;Indian Journal of VLSI Design;2023-03-30

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