Optimizing FPGA Logic Block Architectures for Arithmetic-Reference-Cited by-同舟云学术

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Optimizing FPGA Logic Block Architectures for Arithmetic

Published:2020-06 Issue:6 Volume:28 Page:1378-1391
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Murray Kevin E.^ORCID,Luu Jason,Walker Matthew J. P.,McCullough Conor,Wang Sen,Huda Safeen^ORCID,Yan Bo,Chiasson Charles,Kent Kenneth B.^ORCID,Anderson Jason,Rose Jonathan,Betz Vaughn^ORCID

Funder

Natural Science and Engineering Research Council

Intel

New Brunswick Innovation Foundation

CMC Microsystems

Semiconductor Research Corporation

Texas Instruments

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/9104037/09072274.pdf?arnumber=9072274

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS;Integration;2024-01

2. Fast FPGA-Based Multipliers by Constant for Digital Signal Processing Systems;Electronics;2023-01-26

3. Field-Programmable Gate Array Architecture;Handbook of Computer Architecture;2023

4. Exploring FPGA Logic Block Architecture for Reduced Configuration Memory;Advances in Electrical and Computer Engineering;2022

5. High-performance and low-energy approximate full adder design for error-resilient image processing;International Journal of Electronics;2021-08-31

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