A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/9562994/09513296.pdf?arnumber=9513296
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Ultra8T: A sub-threshold 8T SRAM with leakage detection;Integration;2024-09
2. A Low-Power Variation-Tolerant 7T SRAM With Enhanced Read Sensing Margin for Voltage Scaling;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08
3. A Low Threshold Voltage Ultradynamic Voltage Scaling SRAM Write Assist Technique for High-Speed Applications;Active and Passive Electronic Components;2023-11-07
4. A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10
5. Schmitt-Trigger-Based Low Power SRAM Implemented Using 45-nm CMOS Technology;2023 IEEE Region 10 Symposium (TENSYMP);2023-09-06
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