A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme-Reference-Cited by-同舟云学术

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A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

Published:2011-01 Issue:1 Volume:19 Page:165-170
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Hsu Hsuan-Jung,Huang Shi-Yu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/5673483/05286236.pdf?arnumber=5286236

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Optimization of DCO Using Latch-Based Varactor Cells for a Cell-Based PLL;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

3. A Fast Digital Phase Frequency Detector with Preset Word Frequency Searching in ADPLL for a UHF RFID Reader;Engineering, Technology & Applied Science Research;2022-10-02

4. RTL & Physical Design Flow of Power Efficient Components of All Digital Phase Locked Loop (ADPLL);2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO);2022-04-28

5. A 0.001-mm$$^{2}$$ 112.32-$$\upmu $$W All-Digital PLL with Dual-Tuned DCO and Dual-Tuned Control Algorithm;Circuits, Systems, and Signal Processing;2021-09-17

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