RTL & Physical Design Flow of Power Efficient Components of All Digital Phase Locked Loop (ADPLL)
Author:
Affiliation:
1. Dhirubhai Ambani Institute of Information and Communication Technology,VLSI and Embedded Systems Group,Gandhinagar,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9828864/9828869/09829001.pdf?arnumber=9829001
Reference18 articles.
1. A compact, low-power low-jitter digital PLL
2. An All-Digital PLL for Video Pixel Clock Regeneration Applications
3. An ADPLL circuit using a DDPS for genlock applications
4. An all-digital phase-locked loop (ADPLL)-based clock recovery circuit;hsu;1999 IEEE Journal of Solid-States Circuits,0
5. A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme
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