A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic-Reference-Cited by-同舟云学术

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A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic

Published:2008-03 Issue:3 Volume:16 Page:326-331
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Das S.,Khatri S.P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/4453948/04446775.pdf?arnumber=4446775

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Gecikme, alan, güç ve enerji açısından hibrit paralel toplayıcılar için karşılaştırmalı bir performans değerlendirmesi;Gazi Üniversitesi Mühendislik Mimarlık Fakültesi Dergisi;2023-04-12

2. Performance Investigation of a Modified Hybrid Parallel Prefix Adder for Speedy and Lesser Power Computations;IETE Journal of Research;2022-08-18

3. Analysis of Parallel Prefix Adders with Low Power and Higher Speed;2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC);2022-08-17

4. Area and delay optimized two step binary adder using carry substitution algorithm for FIR filter;Analog Integrated Circuits and Signal Processing;2022-06-16

5. Design of Area Efficient Unified Binary/Decimal Adder/Subtractor Using Triple Carry Based Prefix Adder;2022 8th International Conference on Advanced Computing and Communication Systems (ICACCS);2022-03-25

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