Design of Area Efficient Unified Binary/Decimal Adder/Subtractor Using Triple Carry Based Prefix Adder-Reference-Cited by-同舟云学术

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Design of Area Efficient Unified Binary/Decimal Adder/Subtractor Using Triple Carry Based Prefix Adder

Published:2022-03-25 Issue: Volume: Page:
ISSN:
Container-title:2022 8th International Conference on Advanced Computing and Communication Systems (ICACCS)
language:
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Author:

Krishnan Thiruvenkadam¹,Anguraj Parthibaraj¹,S Saravanan²,A Vidya³,K Sivanandam⁴

Affiliation:

1. K. Ramakrishnan College of Technology,Department of ECE,Trichy,India

2. K S Rangasamy College of Technology,Department of ECE,Tiruchengode,India

3. K. Ramakrishnan College of Engineering,ECE Department,Trichy,India

4. M. Kumarasamy College of Engineering,Department of ECE,Karur,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9784926/9784957/09785045.pdf?arnumber=9785045

Reference15 articles.

1. Design of high-speed RCA based 2-D bypassing multiplier for fir filter

2. Design and implementation of area efficient EAIC modulo adder

3. Design of Low-Area and High Speed Pipelined Single Precision Floating Point Multiplier

4. Area-Efficient Dual-Mode Fused Floating-Point Three-Term Adder

5. Design of Low Power TPG Using LP-LFSR

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and realization of area-efficient approximate multiplier structures for image processing applications;Microprocessors and Microsystems;2023-10

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