Design and implementation of area efficient EAIC modulo adder-Reference-Cited by-同舟云学术

Design and implementation of area efficient EAIC modulo adder

Author:

Krishnan Thiruvenkadam^ORCID,Saravanan S.,Anguraj Parthibaraj,Pillai Anjali S.

Publisher

Elsevier BV

Subject

General Medicine

Reference20 articles.

1. Vedic-based squaring circuit using parallel prefix adders;Jain,2020

4. K. Thiruvenkadam S. Saravanan, Design of Low-Area and High Speed Pipelined Single Precision Floating Point 2020 Coimbatore, India 1259 1264.

5. A novel framework for procedural construction of parallel prefix adders;Kaneko,2019

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