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Design and Implementation of Reconfigurable Asynchronous Pipelines

  • Published:2020-06 Issue:6 Volume:28 Page:1527-1539
  • ISSN:1063-8210
  • Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • language:
  • Short-container-title:IEEE Trans. VLSI Syst.

Author:

de Gennaro AlessandroORCID,Sokolov DanilORCID,Mokhov Andrey

Funder

Engineering and Physical Sciences Research Council (EPSRC) Impact Acceleration Grant Dataflow Computation à la Carte

EPSRC Research

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low power adders using  asynchronous pipelined modified low voltage MCML for signal processing and communication applications;Analog Integrated Circuits and Signal Processing;2024-01-11

2. Asynchronous Circuit Test IP Core Based on OLFSR and FPGA Implementation;2022 2nd International Conference on Computer Science, Electronic Information Engineering and Intelligent Control Technology (CEI);2022-09-23

3. Design and Implementation of Office Automation System Based on Internet of Things Technology;Wireless Communications and Mobile Computing;2022-09-21

4. AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-04

5. Enabling Design Technology Co-Optimization of SRAMs through Open-Source Software;2020 IEEE International Electron Devices Meeting (IEDM);2020-12-12
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