Asynchronous Circuit Test IP Core Based on OLFSR and FPGA Implementation-Reference-Cited by-同舟云学术

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Asynchronous Circuit Test IP Core Based on OLFSR and FPGA Implementation

Published:2022-09-23 Issue: Volume: Page:
ISSN:
Container-title:2022 2nd International Conference on Computer Science, Electronic Information Engineering and Intelligent Control Technology (CEI)
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Author:

Yang Yanfei¹,Cheng Haoliang¹,Lei Qianqian¹,Feng Song¹,Li Lianbi¹

Affiliation:

1. Xi'an Polytechnic University,Department of Microelectronics Science and Engineering,Xi'an,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9950049/9948458/09950089.pdf?arnumber=9950089

Reference24 articles.

1. An FPGA for implementing asynchronous circuits

2. Self-timed field programmable gate array architectures;payne;University of Edinburg,1997

3. Basic gate implementation of speed-independendent circuits;yakovlevy;31st Design Automation Conference,1994

4. Improved linear congruential random number generator;shen;Journal of Tsinghua University (Science and Technology),2009

5. Algorithms to generate pseudo random numbers and comparison;zheng;Journal of Hubei university of technology,2022

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