AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits
Author:
Affiliation:
1. Department of Computer Engineering, Shahed University, Tehran, Iran
2. Department of Electrical Engineering, Shahed University, Tehran, Iran
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/9745276/09675290.pdf?arnumber=9675290
Reference29 articles.
1. Reconfigurable asynchronous pipelines: From formal models to silicon
2. A method to transform synchronous pipeline circuits to bundled-data asynchronous circuits using commercial EDA tools
3. A New Asynchronous Pipeline Architecture of Support Vector Machine Classifier for ASR System
4. Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization
5. Timing Domain Crossing using Muller Pipelines
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