Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation

Author:

You HengORCID,Yuan Jia,Yu Zenghui,Qiao ShushanORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 17 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and implementation of low power D flip flop for embedded application;PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON MATHEMATICAL SCIENCES AND TECHNOLOGY 2022 (MATHTECH 2022): Navigating the Everchanging Norm with Mathematics and Technology;2024

2. CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

3. Advancements in Binary Number Processing: Analyzing a CNTFET-Based Digital Circuit for 3-Bit Up and Down Counting with Challenges in Artificial Intelligence;2023 International Conference on Sustainable Communication Networks and Application (ICSCNA);2023-11-15

4. High Performance Design of Single Edge Triggered Johnson Counter;2023 4th IEEE Global Conference for Advancement in Technology (GCAT);2023-10-06

5. Design and Implementation of Low-Power and Area-Efficient Flip Flop with Redundant Pre-Charge Free Operation;2023 4th International Conference on Smart Electronics and Communication (ICOSEC);2023-09-20

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