CMOS VLSI Implementation of Implicit Pulsed Dual Edge Triggered Flip Flop using Pass Transistor Logic for Power Efficient Applications-Reference-Cited by-同舟云学术

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CMOS VLSI Implementation of Implicit Pulsed Dual Edge Triggered Flip Flop using Pass Transistor Logic for Power Efficient Applications

Published:2024-05-03 Issue: Volume:17 Page:1019-1023
ISSN:
Container-title:2024 4th International Conference on Pervasive Computing and Social Networking (ICPCSN)
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Author:

Nagarajan P.¹,Ashokkumar N.²,Thandapani Kavitha³,Manimaran B.⁴,Krishnamurthy M.⁵,Kabilamani P.¹

Affiliation:

1. SRM Institute of Science and Technology, Vadapalani,Chennai,Tamilnadu,India

2. Mohanbabu University (Erstwhile Sree Vidyanikethan Engineering College),Tirupati,AndraPradesh

3. Vel Tech Rangarajan Dr Sagunthala R&D Institute of Science and Technology,Chennai,TamilNadu,India

4. Rajalakshmi Institute of Technology, Kuthambakkam,Chennai,Tamilnadu,India

5. PSNA College of Engineering and Technology,Dindigul,Tamilnadu,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10607378/10607379/10607705.pdf?arnumber=10607705

Reference15 articles.

1. Weste and Kamaran Eshraghian;Neil;Princinles of CMOS VLSI Design: A System perspective,2003

2. Design of Sequential Elements for Low Power Clocking System

3. Practical Low Power Digital VLSI Design

4. Design of power gated double edge triggered flip flop using sleep transistor technique (PG-STDETFF);Nagarajan;The patent office journal, Government of India,2017

5. A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

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