The Effects of Races, Delays, and Delay Faults on Test Generation

Author:

Breuer M.A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Harzard-Based ATPG for Improving Delay Test Quality;Journal of Electronic Testing;2015-01-11

2. Impact of Hazards on Pattern Selection for Small Delay Defects;2009 15th IEEE Pacific Rim International Symposium on Dependable Computing;2009-11

3. Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits;IEEE Transactions on Computers;2009-03

4. Path delay fault simulation of sequential circuits;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2000-04

5. On variable clock methods for path delay testing of sequential circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;1997

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