Author:
Chakraborty T.J.,Agrawal V.D.,Bushnell M.L.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
4 articles.
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1. Delay Fault Testing of VLSI Circuits;Test Generation of Crosstalk Delay Faults in VLSI Circuits;2018-09-21
2. Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2006-12
3. Efficient path-delay fault simulation for standard scan design;IEE Proceedings - Circuits, Devices and Systems;2002-12-01
4. Path-delay fault simulation for circuits with large numbers of paths for very large test sets;Proceedings. 21st VLSI Test Symposium, 2003.