A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration-Reference-Cited by-同舟云学术

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A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration

Published:2021-04 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Papistas I. A.,Cosemans Stefan,Rooseleer Bram,Doevenspeck Jonas,Na M.-H.,Mallik Arindam,Debacker Peter,Verkest Diederik

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9431363/9431390/09431575.pdf?arnumber=9431575

Cited by 28 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors;Journal of Real-Time Image Processing;2024-07-31

2. Novel SRAM based Temporary Memory for PVT Variation Tolerant Analog In-Memory Computing;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. Massive MIMO Signal Detection using SRAM-based In-Memory Computing;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

4. A 2-to-10-b Output Precision Reconfigurable Compute-In-Memory Macro Leveraging Input Conditioning Using Residue Amplification;IEEE Solid-State Circuits Letters;2024

5. Analog or Digital In-Memory Computing? Benchmarking Through Quantitative Modeling;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

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