A 2-to-10-b Output Precision Reconfigurable Compute-In-Memory Macro Leveraging Input Conditioning Using Residue Amplification-Reference-Cited by-同舟云学术

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A 2-to-10-b Output Precision Reconfigurable Compute-In-Memory Macro Leveraging Input Conditioning Using Residue Amplification

Published:2024 Issue: Volume:7 Page:219-222
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Vijayakumar Balaji¹^ORCID,Sundar Ashwin Balagopal¹^ORCID,Viraraghavan Janakiraman¹^ORCID,Bharadwaj Varchas¹

Affiliation:

1. Indian Institute of Technology Madras, Chennai, India

Funder

Ministry of Electronics and Information Technology, Government of India

Centre for RF, Analog, and Mixed-Signal ICs, IIT Madras

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/8011414/10359146/10559382.pdf?arnumber=10559382

Reference9 articles.

1. IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm² CIM-SRAM With Multi-Bit Analog Batch-Normalization

2. A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration

3. A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks

4. A 35.5-127.2 TOPS/W Dynamic Sparsity-Aware Reconfigurable-Precision Compute-in-Memory SRAM Macro for Machine Learning

5. 15.2 A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating

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