Thermal characteristics analysis and optimization of 3D-Stacked Memory Packaging
Author:
Affiliation:
1. Guilin University of Electronic Technology,School of Mechanical and Electrical Engineering,Guilin,China,541004
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10070854/10070925/10071101.pdf?arnumber=10071101
Reference6 articles.
1. Thermal modeling and analysis of advanced 3D stacked structures[C];vaddina;Elsevier International Conference on Communication Technology and System Design,2011
2. Study on predicting the temperature of stacked chip based on thermal resistance matrix[C];zhang;24th International Symposium on the Physical and Failure Analysis of Integrated Circuits July 4 - 7 2017,2017
3. Experimental and numerical study of 3D stacked dies under forced air cooling and water immersion cooling
4. Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit[J];samson;Microelectronics Journal,2015
5. Research on Flip-Chip Bonding Process and Thermal Cycle Reliability Simulation of 3-D Stacked Structure
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