Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit-Reference-Cited by-同舟云学术

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Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit

Published:2015-12 Issue:12 Volume:46 Page:1106-1113
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Melamed Samson,Imura Fumito,Nakagawa Hiroshi,Kikuchi Katsuya,Hagimoto Michiya,Matsumoto Yukoh,Aoyagi Masahiro

Publisher

Elsevier BV

Subject

General Engineering

Reference19 articles.

1. Power-constrained CMOS scaling limits;Frank;IBM J. Res. Dev.,2002

2. S. Melamed, T. Thorolfsson, T.R. Harris, S. Priyadarshi, P. Franzon, M.B. Steer, W.R. Davis, Thermal analysis of 3-d integrated circuits using high definition power blurring 31 (5) (2012) 676–689.

3. C. Torregiani, B. Vandevelde, H. Oprins, E. Beyne, I. De Wolf, Thermal analysis of hot spots in advanced 3D-stacked structures, In: Proceedings of 15th International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2009, 2009, pp. 56–60.

4. A novel method of hotspot temperature reduction for a 3D stacked CMOS IC chip device fabricated on an ultrathin substrate;Kato;J. Micromech. Microeng.,2013

5. S. Mysore, B. Agrawal, N. Srivastava, S.-C. Lin, K. Banerjee, T. Sherwood, Introspective 3D chips, In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, San Jose, California USA, 2006, pp. 264–273.

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1. Die level thinning after bonding on the substrate in 3D packaging;Journal of Physics: Conference Series;2023-03-01

2. Thermal characteristics analysis and optimization of 3D-Stacked Memory Packaging;2022 19th China International Forum on Solid State Lighting & 2022 8th International Forum on Wide Bandgap Semiconductors (SSLCHINA: IFWS);2023-02-07

3. Effect of different temperature distribution on multi-stack BGA package;Microelectronics International;2021-02-26

4. R&D of 3D-IC Technology for the AI·IoT Era;Vacuum and Surface Science;2019-11-10

5. Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-10

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