Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit

Author:

Melamed Samson,Imura Fumito,Nakagawa Hiroshi,Kikuchi Katsuya,Hagimoto Michiya,Matsumoto Yukoh,Aoyagi Masahiro

Publisher

Elsevier BV

Subject

General Engineering

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Die level thinning after bonding on the substrate in 3D packaging;Journal of Physics: Conference Series;2023-03-01

2. Thermal characteristics analysis and optimization of 3D-Stacked Memory Packaging;2022 19th China International Forum on Solid State Lighting & 2022 8th International Forum on Wide Bandgap Semiconductors (SSLCHINA: IFWS);2023-02-07

3. Effect of different temperature distribution on multi-stack BGA package;Microelectronics International;2021-02-26

4. R&D of 3D-IC Technology for the AI·IoT Era;Vacuum and Surface Science;2019-11-10

5. Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-10

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