Automatic Verification Platform Based on RISC-V Architecture Microprocessor
Author:
Affiliation:
1. Fudan University,School of Information Science and Technology,Shanghai,China
2. Institute of Microelectronics,Chinese Academy of Sciences,Beijing,China
3. Fudan University,Academy of Engineering and Technology,Shanghai,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9757913/9757914/09757978.pdf?arnumber=9757978
Reference6 articles.
1. Simulation and Formal: The Best of Both Domains for Instruction Set Verification of RISC-V Based Processors
2. UVM Based Testbench Architecture for Coverage Driven Functional Verification of SPI Protocol
3. The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0
4. Review on Development of Domestic Embedded Processor;deng;Aeronautical Computing Technique,2021
5. A Study of Performance and Power Consumption Differences Among Different ISAs
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1. RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32;2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM);2023-10-10
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