RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32-Reference-Cited by-同舟云学术

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RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32

Published:2023-10-10 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM)
language:
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Author:

Nascimento Felipe F.¹,Wuerdig Rodrigo N.²,Ponchet André F.¹,Sanches Bruno³,Loubach Denis S.⁴,D’Amore Roberto¹,Junior Marcus H. Victor¹,Oliveira Walter S.¹,Kuribara Vitor O.¹,Moreira Luiz C.¹

Affiliation:

1. Aeronautics Institute of Technology,Electronic Engineer Division IEEA,São José dos Campos,Brazil

2. UFRGS,Graduate Program on Microelectronics,Porto Alegre,Brazil

3. University of São Paulo,Department of Electronic Systems,São Paulo,Brazil

4. Aeronautics Institute of Technology,Department of Computer Systems,São José dos Campos,Brazil

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10308946/10308798/10309011.pdf?arnumber=10309011

Reference18 articles.

1. Automatic Verification Platform Based on RISC-V Architecture Microprocessor

2. Github - wuxx/icesugar-nano: icesugar-nano FPGA board (base on iCE40LP1K);w,0

3. Risc-v software source code,2023

4. Github - BrunoLevy/learn-fpga: Learning FPGA, yosys, nextpnr, and RISC-V;b,2023

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