A COMPARISON OF SILICON AND III–V TECHNOLOGY PERFORMANCE AND BUILDING BLOCK IMPLEMENTATIONS FOR 10 AND 40 Gb/s OPTICAL NETWORKING ICs

Abstract

Scalable models for both active and passive components are essential for the design of highly integrated fiber–optic physical layer ICs. This paper focuses on the various technology options available of 10 Gb/s and 40 Gb/s applications, on how their constituent components are modeled and what the characteristics and requirements are for the basic building blocks. As part of the technology comparison, an overview of the performance of leading edge Si CMOS, SiGe BiCMOS and III–V technologies is presented. Scalable models for SiGe HBTs and GaAs p–HEMTs are then compared with measured data for various device sizes. Inductors, varactors, transmission lines and isolation techniques on Si and III–V substrates are discussed next followed by technology–specific implementations of VCO and digital building blacks. Finally, Transimpedance Limiting Amplifier (TIALA) as well as laser and modulator driver designs in SiGe BiCMOS, InP HBT and GaAs p–HEMT processes using scalable device models are illustrated for 10 and 40 Gb/s fiber-optics applications.