An Energy-Efficient Switching Scheme for Low-Power SAR ADC Design

Author:

Liang Yuhua1,Zhu Zhangming1

Affiliation:

1. School of Microelectronics, Xidian University, 2 South Taibai Road, Xi'an, Shaanxi, Xi'an 710071, P. R. China

Abstract

A novel energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC) is proposed in this paper. The average switching energy of the proposed switching scheme can be reduced by 95.3%, compared with the [Formula: see text]-based scheme. Moreover, the linearity has been also improved significantly. Employing the proposed switching scheme, a 10-bit 100[Formula: see text]kS/s SAR ADC is designed in SMIC 0.18-[Formula: see text]m CMOS process. At a 0.6-V supply, the ADC consumes 43.7[Formula: see text]nW. Consequently, the figure-of-merit (FOM) is optimized to 0.58[Formula: see text]fJ/conversion-step.

Funder

the National Natural Science Foundation of China

the China Postdoctoral Science Foundation

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

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