CFA: Toward the Realization of Conservative Full Adder in QCA with Enhanced Reliability

Abstract

The significant physical challenges of Complementary Metal Oxide Semiconductor (CMOS) technology drives it on the brink of ultimate limit. With the surfacing of tremendous research findings, Quantum dot cellular automata (QCA) has emerged as a new technology in nanoscale era as a viable alternative to CMOS technology. Besides its wide acceptance, QCA-based nanoscale circuits are highly susceptible to huge fault/error rates. Thus, the fault tolerance and testability have become the utmost necessity for ensuring reliable QCA circuit. Toward this direction, conservative logic plays a vital role to achieve such reliability. In this paper, a Conservative Full Adder (CFA) is proposed with a simplified testable logic to detect the internal fault in the circuit. A simple majority–minority-based testing logic in the circuit is augmented for the detection of conservative (bit preserving) nature. Besides the testable feature, the full adder is chosen for its versatility in Arithmetic and Logic Unit (ALU) synthesis. Experimental result establishes the superiority of the proposed logic in terms of design capability as well as testability. Also, a comprehensive analysis of energy dissipation is performed to ensure the robustness of the proposed testable conservative adder. The QCA layout design and functional verification of the design are performed using the QCADesigner tool and Hardware Description Language for QCA (HDLQ) tool, respectively. The QCAPro simulator is used to evaluate the energy dissipation of the circuit.