Cost-efficient method for inverter reduction and proper placement in quantum-dot cellular automata-Reference-Cited by-同舟云学术

Cost-efficient method for inverter reduction and proper placement in quantum-dot cellular automata

Published:2022-12-13 Issue: Volume: Page:1-34
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Pramanik Amit Kumar¹²^ORCID,Pal Jayanta³^ORCID,Mohit Kumar⁴,Goswami Mrinal⁵^ORCID,Sen Bibhash²^ORCID

Affiliation:

1. Dept. of Computer Science & Engineering, Dumka Engineering College, Dumka, India

2. Department of Computer Science & Engineering, NIT Durgapur, Durgapur, India

3. Department of Information Technology, Tripura University, Suryamaninagar, India

4. Department of Computer Science, ETH Zurich, Zurich, Switzerland

5. Department of Systemics, School of Computer Science, UPES, Dehradun, India

Funder

Young Faculty Research Fellowship (YFRF) of the Visvesvaraya Ph.D. scheme

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2022.2145503

Reference58 articles.

1. The design and implementation of a robust single-layer QCA ALU using a novel fault-tolerant three-input majority gate

2. Synthesis of combinational logic using three-input majority gates

3. Banerjee, A., Mahato, D. K., Choudhuri, S., Dey, M. & Chakraborty, R. (2018). Performance evaluation of controlled inverter using quantum dot cellular automata (qca).

4. Use of Symmetric Functions Designed by QCA Gates for Next Generation IC

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Synthesis of Fault-Tolerant QCA Logic Circuit Using Cellular Automata;Communications in Computer and Information Science;2024

2. Design and Analysis of Regular Clock Based 2:4 Decoder Using T-Gate in QCA;Advances in Intelligent Systems and Computing;2023