Exploration of Word Width and Cluster Size Effects on Tree-Based Embedded FPGA Using an Automation Framework

Abstract

This paper introduces a novel framework that automates and accelerates the development of embedded Field Programmable Gate Arrays (eFPGAs). The proposed solution is considered as the first environment for tree-based eFPGA implementation including software, hardware and loader. The developed framework allows users to generate eFPGA architecture in the form of hardware description language using Physical Design Flow (PDF) tool. It is a powerful tool that can produce a wide variety of designs ranging from small eFPGA to complex eFPGA. The bit file description of practical application is done in parallel, simultaneously and rapidly by the suggested Computer Aided Design (CAD) tools. The Loader, called Multi-Level Loader (MLL), is also provided to inject the bits into the corresponding SRAMs. Our framework is widely explored by modifying the data width. This research proves that data width equal to 17 has the best trade-off between performance, area and static power. However, it is penalized for buses having data length greater than 32. The experimentation demonstrates that a data width equal to 12 is the best for a 32-bit bus. Automation and significant acceleration of the eFPGA development cycle are also achieved in this study. A set of bench-marking applications with various multi-use purposes is mapped. The experimental results show the efficiency and flexibility of the proposed framework.