Energy-Aware Schedules Under Chip Reliability Constraint for Multi-Processor Systems-on-a-Chip

Abstract

Even though multi-core systems are effective architectures to overcome the limitation of single-core systems, techniques to improve reliability, throughput and power consumption are highly needed. With the increasing complexity of multi-processor systems-on-a-chip (MPSoCs) to handle the ever increasing complexity of embedded computing applications, the reliability of such systems is now a big concern in the industry. Complex MPSoCs typically have multiple execution modes with different throughput and reliability performances. These complex embedded systems are also expected to perform under minimum power and energy consumptions. In this paper, we present efficient techniques for low-energy and thermal-aware schedules that meet the deadlines under chip reliability constraints. The presented techniques under different objective functions are implemented and executed on multiple embedded applications under multiple underlying system architectures to show the performance and efficiency of the techniques.