Evaluation and validation of efficient hierarchical interconnection in multi-processor system on chip
Author:
Affiliation:
1. School of Information and Electronic Engineering (Sussex Artificial Intelligence Institute), Zhejiang Gongshang University, Hangzhou, Zhejiang, China
Funder
no funding associated with
Publisher
Informa UK Limited
Link
https://www.tandfonline.com/doi/pdf/10.1080/23335777.2024.2326931
Reference36 articles.
1. Resource management for improving the overall reliability of multiprocessor systems-on-chip;Ma Y;Depend Embed Syst,2021
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3. GMMSO: game model-combined improved moth search optimization approach for reconfigurable asymmetric multi-processor system-on-chip architecture
4. A communication-aware and predictive list scheduling algorithm for network-on-chip based heterogeneous muti-processor system-on-chip
5. Aghapour E, Zhang Y, Pathania A, et al. Pipelined CNN Inference on Heterogeneous Multi-processor System-on-Chip. In Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing: Software Optimizations and Hardware/Software Codesign. Cham: Springer Nature Switzerland; p. 405–427.
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