1. A. Hemani, A. Jantsch, S. Kumar, A. Postula, and J. Öberg, “Network on a Chip : an Architecture for Billion Transistor Era.”.
2. A network on chip architecture and design methodology;Kumar;Proc. IEEE Comput. Soc. Annu. Symp. VLSI, ISVLSI,2002
3. Communication contention in task scheduling;Sinnen;IEEE Trans. Parallel Distr. Syst.,2005
4. Some simplified NP-complete problems;Garey,1974
5. NP-complete scheduling problems;Ullman;J. Comput. Syst. Sci.,1975