Technology Scaling Roadmap for FinFET-Based FPGA Clusters Under Process Variations

Abstract

The technology scaling impact on FinFET-based Field-Programmable Gate Array (FPGA) components (Flip-Flops and Multiplexers) and cluster metrics is evaluated for technology nodes starting from 20[Formula: see text]nm down to 7[Formula: see text]nm. Power consumption, delay and energy (Power Delay Product, or PDP) trends are reported with FinFET technology scaling. Cluster metrics are then evaluated based on three benchmarking circuits: 2-bit adder, 4-bit NAND and cascaded flip-flops chain. The study shows that power, delay and PDP of the FPGA cluster are improved as we scale down the technology. An example for improvement is that for 7[Formula: see text]nm 2-bit adder, circuit speed is 15% higher than its value at 20[Formula: see text]nm and PDP at 7[Formula: see text]nm is reduced by 43% compared to its value at 20[Formula: see text]nm. The impacts of temperature and threshold voltage variations on FPGA cluster performance are also reported after evaluating a 2-bit adder circuit as a benchmark which is then used to calculate the design constraints to meet 99.9% yield percentage.