Particle Swarm Optimization Design of Low-Power Multistage Amplifier using gm/ID Methodology

Author:

Zhang Gengyu1ORCID,Xiao Xia1,Xu Jiangtao1,Nie Kaiming1,Gao Zhiyuan1

Affiliation:

1. School of Electronic and Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin, 300072, China

Abstract

A design flow using the [Formula: see text]/[Formula: see text] methodology with the adaptive particle swarm optimization (PSO) algorithm is proposed for the modern analog circuit in this paper. For the advanced CMOS process, [Formula: see text]/[Formula: see text] methodology is suitable to the long channel and short channel design in all transistor operation regions. Different from the classical PSO algorithm, the adaptive PSO algorithm features the better search efficiency and faster convergence speed over the global search. Two amplifiers were designed and implemented in a standard 0.11[Formula: see text][Formula: see text]m CMOS process using MATLAB and HSPICE. Using the thermal noise coefficient [Formula: see text] and the corner frequency [Formula: see text], this paper explored the noise design budget of low-power multistage amplifier in different saturation modes. Detailed optimization of the objective function and constraints are classified into the mono-objective case and the multi-objective case. The total running times of simulations are 5649 s and 6813 s while the errors are less than 9% and 10%, respectively. Compared with CODE, GA[Formula: see text]PF and DE[Formula: see text]PF algorithms, it can save more running time and improve the accuracy of the design. Moreover, it provides more design freedom for the trade-off among gain, the gain-bandwidth (GBW) product, noise and the phase margin under worst cases without extra tweaking. Not only can the methodology work in the 0.18[Formula: see text][Formula: see text]m CMOS process, but also be migrated to the 0.11[Formula: see text][Formula: see text]m CMOS process, even in the nanometer analog circuit.

Funder

National Natural Science Foundation of China

Tianjin Science and Technology Development Project

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. High-Dimensional Bayesian Optimization for Analog Integrated Circuit Sizing Based on Dropout and gm/ID Methodology;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-11

2. Design framework for inverter cascode transimpedance amplifier using Gm/ID based PSO applying design equations;AEU - International Journal of Electronics and Communications;2021-12

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